Electronic components such as integrated circuits, including memory chips, often fail due to flaws resulting from the manufacturing process. Indeed, even as manufacturing processes are improved to reduce defect rates, increasingly complex chip designs require finer and finer circuitry, pushing the limits of the improved manufacturing processes and increasing the potential for defects. Electronic components are commonly subjected to an initial wafer probe test after production of the wafer from which the components are separated, in order to detect catastrophic or “killer” defects in their circuitry. Wafer probe testing, however, typically will not detect less severe or “latent” defects in the circuitry that may nevertheless result in early-life failure or “infant mortality” of a component.
Although the percentage of electronic components such as memory chips and integrated circuits that are manufactured with latent defects may be relatively small (for example on the order of 1-4%), many modern electronic devices incorporate up to fifty or more such components. Early-life failure of any one of these components may destroy or significantly degrade the performance of the overall device. As a result, even a small percentage of latent defects in the components can produce an undesirably high rate of failure in the assembled device.
In order to reduce the incidence of infant mortality and thereby increase reliability, many manufacturers subject their components to accelerated life-cycle testing, referred to as stress testing or “burn-in”. During burn-in, some or all of the components produced are stress-tested by subjecting them to elevated temperature, voltage, and/or other non-optimal condition(s) in order to precipitate component failure resulting from latent defects that were not identified by the initial wafer probe testing. Due to their very fine circuitry, however, many modern electronic components cannot withstand severe burn-in conditions without incurring damage, even to components that initially had no latent defects. As a result, stress tests must now typically be performed more gently, for example using lower temperature and/or voltage conditions, thereby requiring longer duration burn-in periods to identify latent defects. In addition, the stress testing conditions often must be very carefully and precisely controlled. For example, because different chips within even a single production run may generate differing amounts of heat during operation, burn-in of some types of chips requires the provision of separate and individually temperature-controlled burn-in chambers for each chip being tested. Due to the increased complexity and duration, the stress test or burn-in process represents a significant portion of the expense of many modern electronic components.
In order to reduce the time and expense of component burn-in, a “binning” system and method have been developed. In many instances, both killer and latent defects result from like or related causes. For example, a dust particle may interrupt a conductive path entirely, resulting in a killer defect; or it may interrupt a conductive path only partially, resulting in a latent defect that passes the initial wafer probe test but produces an early life failure. Because many causes of killer and latent defects are localized, both types of defects are often found to cluster in regions on a wafer. As a result, it has been discovered that a component is more likely to have a defect if its neighboring components on the wafer also have defects. For example, a component that passes wafer-probe testing is more likely to have a latent defect if one or more of its neighboring components on the wafer are found to have killer defects than if all of its neighboring components on the wafer also pass wafer-probe testing. And it has been discovered that the likelihood of a component that passes wafer-probe testing having a latent defect increases with the number of neighboring components that fail wafer-probe testing. By “binning” those components that pass wafer-probe testing into separate groups depending on how many of its neighbors failed wafer-probe testing, the components are separated into groups expected to have greater or lesser degrees of early life reliability. For example, as seen with reference to FIG. 1, a wafer 10 contains a plurality of components or die. Some of the die on wafer 10 contain killer defects, indicated with an “X”, which will fail the wafer-probe test. The remaining die do not contain killer defects, but may contain latent defects. Die without killer defects may be categorized depending on the number of neighboring die that have killer defects. For example, die A has five immediately adjacent neighbors found to have killer defects, die B has one immediately adjacent neighbor found to have a killer defect, and die C has no immediately adjacent neighbors found to have killer defects. Die categorized in this manner may then be binned according to the number of immediately adjacent neighbors found to have killer defects. For example, if the eight immediately adjacent neighboring die on the wafer 10 are considered, each die will have between zero and eight neighbors with killer defects. As shown in FIG. 2, die such as C, with no neighbors having killer defects, will be placed in bin 0; die such as B, with one neighbor having a killer defect, will be placed in bin 1; die with two neighbors with killer defects will be placed in bin 3; and so on.
Since defects (killer and latent) tend to cluster in regions on the wafer, die in bin 0 will be statistically the least likely to have latent defects, whereas die in bin 8 will be statistically the most likely to have latent defects. Die in the successive intermediate bins 2-7 will have progressively greater statistical likelihood of having latent defects. By burn-in testing a representative sample of dies from each of the bins 1-8 (“sample burn-in”), the statistical likelihood of latent defects for all die within each respective bin can be estimated. The remaining die in those bins having a statistically-estimated likelihood of latent defect that is lower than the specified failure-in-time (“FIT”) rate (the maximum rate of burn-in failure deemed acceptable) need not be individually burned in, since on average they will meet or exceed the desired reliability. The remaining die in those bins having a statistically-estimated likelihood of latent defect that is higher than the specified FIT rate may be subjected to individual burn-in testing. Although binning and sample burn-in can reduce the cost of burn-in testing by eliminating the need to individually test some of the die (namely those die remaining in bins having a statistically-estimated likelihood of latent defect that is lower than the specified FIT rate after sampling), burn-in costs can still be significant since a statistically significant sample of die from each bin must be tested. These costs can add considerably to the cost of component manufacture. Thus, it can be seen that needs exist for improved systems and methods for determining the reliability of electronic components and other devices including integrated circuits and memory chips. It is to the provision of improved systems and methods for determining the reliability of electronic components and other devices meeting these and other needs that the present invention is primarily directed.